1. Field of the Invention
The present invention relates generally to EEPROM transistor cell memories, and more particularly to a nonvolatile single EEPROM transistor cell memory divided into sectors having sector erase, and providing for the transfer of data to the cells by way of the word lines, resulting in bit line sector page programing.
2. Description of the Prior Art
Electrically Erasable Programmable memories are well known in the art. In "A Million-Cycle CMOS 256K EEPROM" by D. Cioaca et al, IEEE Journal of Solid State Circuits, Vol. SS-22, No. 5, Oct. 1987, a device is described using a two transistor cell for each bit of information. The memory cell state selection in this type of device is achieved by Fowler-Nordheim tunneling of charges between a floating gate and a silicon substrate through a very thin dielectric, or between the floating gate and control gate through the interpoly oxide. EEPROM memories using Fowler-Nordheim tunneling only require a single external power supply providing 5 volts or 3 volts. The higher voltages necessary for programming can be produced internally. Although the use of a single power supply is an advantage, two transistors per memory cell are needed, making them relatively expensive.
Another type of device, known as "Flash EPROM" is disclosed in U.S. Pat. No. 4,698,787 and uses only one transistor per cell. It is programmed like an EPROM and is erased like a EEPROM, but requires a high programming current which makes it difficult to use. In addition, the mechanism used to program the Flash EPROM causes hole trapping in the dielectric separating the floating gate from the substrate. The trapped holes lead to inadvertent electron tunneling from the floating gate, resulting in destruction of stored data.
An approach using a single EEPROM transistor cell is disclosed by Hakaiama et al in "A-5V-Only One Transistor 256K EEPROM with Page-Mode-Erase", IEEE Journal of Solid State Circuits, Vol 24, No.4, August 1989. Fowler-Nordheim tunneling is used for both the erase and write operations. Unfortunately, the cell size is larger than the Flash EPROM cell because for every bit line a separate metal line for VSS is required.
Another similar device is disclosed by McConnel et al in "AN Experimental 4 Mb Flash EEPROM With Sector Erase", IEEE Journal of Solid State Circuits, Vol. 26, No. 4, April 1991. As in the Hakaiama approach, a separate VSS line is required for every bit line, resulting in the cell size being larger than in the Flash EPROM cell.
Momodoni et al in "A 4 Mb NAND EEPROM With Tight Programmed VT Distribution", IEEE Journal of Solid State Circuits, Vol.26, No. 4, April 1991, reveals a device with EEPROM cells connected in series. The series connection has the advantage of small size, but results in slow memory speed due to an excessively small cell current during the read operation.